Partitioning and macromodeling -based realizable reduction of interconnect circuit models

Aalto University, P.O. Box 11000, FI-00076 Aalto www.aalto.fi Author Pekka Miettinen Name of the doctoral dissertation Partitioning and macromodeling -based realizable reduction of interconnect circuit models Publisher School of Electrical Engineering Unit Department of Radio Science and Engineering Series Aalto University publication series DOCTORAL DISSERTATIONS 10/2014 Field of research Circuit Theory Manuscript submitted 4 November 2013 Date of the defence 21 February 2014 Permission to publish granted (date) 17 December 2013 Language English Monograph Article dissertation (summary + original articles) Abstract With advancing technology of integrated circuits, the interconnects and their non-ideal parasitics between active elements play an increasingly important role for the signal behavior. In a typical design flow, extraction tools are often used to generate a circuit netlist from the original chip topology for post-layout verification simulations. To reach desired accuracy, the interconnects and their parasitics need to be modeled with high precision that generates huge RLCK netlists, which in turn poses significant run-time and memory problems for the design process. One avenue to speed up the verification step is to apply model-order reduction (MOR) algorithms to the extracted netlists attempting to model the system with a reduced-size representation. This thesis details the research of partitioning and macromodel-based MOR approach for linear RLCK circuits. Using partitioning in MOR to first divide the circuit into smaller subcircuits makes it possible to use low-order approximations per each partition and still retain a good overall approximation accuracy for the total reduced circuit, when the individually reduced partitions are recombined. This use of low-order approximations in turn guarantees numerical stability and allows the approximations to be matched with relatively simple positive-valued RLCK macromodels, resulting in a realizable RLCK-in–RLCK-out reduction. Partitioning is known to provide the MOR also many other benefits, such as block-level sparsity, facilitated terminal node handling, reduced computational memory demands, and an option for natural parallel processing. Thanks to the many desirable features provided, this thesis aims to show that the presented MOR approach is highly efficient and well comparable to previously published MOR methods, especially in the case of typical interconnect RLCK circuits. The publications of this thesis first discuss the development of efficient RC and RL MOR methods, and the hierarchical approach to MOR offered by partitioning. Then, an RLC MOR method, PartMOR, using the same approach is presented. The latter four publications of this thesis focus on refining the presented methods and solving common difficulties in MOR: Singularity-generating structures in the original circuit can be avoided by isolating such structures with partitioning. Dense coupling of mutual inductances and capacitances between interconnects can be reduced with partitioning and a two-stage approximation. Finally, combining the presented methods together results in a complete RLCK-in–RLCK-out MOR algorithm package.With advancing technology of integrated circuits, the interconnects and their non-ideal parasitics between active elements play an increasingly important role for the signal behavior. In a typical design flow, extraction tools are often used to generate a circuit netlist from the original chip topology for post-layout verification simulations. To reach desired accuracy, the interconnects and their parasitics need to be modeled with high precision that generates huge RLCK netlists, which in turn poses significant run-time and memory problems for the design process. One avenue to speed up the verification step is to apply model-order reduction (MOR) algorithms to the extracted netlists attempting to model the system with a reduced-size representation. This thesis details the research of partitioning and macromodel-based MOR approach for linear RLCK circuits. Using partitioning in MOR to first divide the circuit into smaller subcircuits makes it possible to use low-order approximations per each partition and still retain a good overall approximation accuracy for the total reduced circuit, when the individually reduced partitions are recombined. This use of low-order approximations in turn guarantees numerical stability and allows the approximations to be matched with relatively simple positive-valued RLCK macromodels, resulting in a realizable RLCK-in–RLCK-out reduction. Partitioning is known to provide the MOR also many other benefits, such as block-level sparsity, facilitated terminal node handling, reduced computational memory demands, and an option for natural parallel processing. Thanks to the many desirable features provided, this thesis aims to show that the presented MOR approach is highly efficient and well comparable to previously published MOR methods, especially in the case of typical interconnect RLCK circuits. The publications of this thesis first discuss the development of efficient RC and RL MOR methods, and the hierarchical approach to MOR offered by partitioning. Then, an RLC MOR method, PartMOR, using the same approach is presented. The latter four publications of this thesis focus on refining the presented methods and solving common difficulties in MOR: Singularity-generating structures in the original circuit can be avoided by isolating such structures with partitioning. Dense coupling of mutual inductances and capacitances between interconnects can be reduced with partitioning and a two-stage approximation. Finally, combining the presented methods together results in a complete RLCK-in–RLCK-out MOR algorithm package.